New Packaging and Interconnect Technologies for Ultra Thin Chips

This paper shows different approaches to use the availability of ultrathin chips for the realization of new packages with high density and improved performance. For several years technologies have been developed for the embedding of chips in circuit boards in order to achieve 3D-packages using conventional processes from PCB manufacturing. Ultrathin chips are suited to be integrated in rigid circuit boards as well as on and in multilayer flexible substrates. The use of interposers prior to embedding can facilitate the embedding of components with ultra fine pitches. An example for a complex RFID-based product will be shown which is enabled by the integration of ultrathin dies. INTRODUCTION A visionary approach for the future production of printed circuit boards was the development of integration technologies for active and passive components in the different layers of the boards. This enables extremely high density of functionality and components in 3 dimensions. The goal is to achieve this progress while maintaining the processes typical for PCB manufacturing. Different approaches have been described for the embedding in FR4 [1,2]. A suitable solution for the integration of chips with very fine pitch is the iBoard technology [3]. It is based on the flip-chip assembly of the fine pitch chips on thin interposers with fan out design. Besides the rigid organic substrates flexible circuits become increasingly important in PCB industry for applications ranging from consumer products to medical implants. Recent developments – e.g. in the project SHIFT [4,5] – allow the integration of components also in multilayer flex substrates which allows an even higher density with low overall thickness. The technologies which are the prerequisites for this solution and experimental results are shown in this paper. Important aspects which were investigated for the different new technologies are the constraints regarding pitch and chip geometries [6]. In order to be embedded in a substrate the components have to be thin. For the integration in rigid circuit boards, 50 μm chip thickness were chosen, for the flexible substrates 20 μm are required. TECHNOLOGIES Ultrathin Chips The wafer thinning is a commonplace procedure in front end wafer fabrication. Typically wafers are thinned down to 120 or 80 μm thickness before dicing into single chips and subsequent packaging. Using commercial thinning services wafer thicknesses of 50 μm are also readily available. Thinning below 50 μm, however, still is critical. This regime is therefore called ultra thin. Wafer handling and dicing becomes more subtle. Micro cracks at edges and corners of chips which may be induced by mechanical dicing are prone to propagate into the bulk of the chips and cause failure. This is especially critical for processes with high mechanical loads like flip chip bonding. For ultra thin chips it is therefore advisable to use a dicing by thinning technique, were separation grooves are etched into the wafer prior to grinding. In the present studies chips with a thickness of 50 μm for FR4 and 20 μm for flexible multilayers have been used to develop and investigate the performance of two distinct embedding technologies. Details of the thinning process and the encountered problems have been the topic of several publications [7,8] will not be presented and discussed in the present paper. Assembly of Ultrathin Chips It has been shown that ultrathin chips are suitable for flipchip processes [9]. Especially in combination with flexible substrate it is important to achieve thin flip-chip contacts in similar dimensions as the two contact partners. For chips and substrates down to 10 μm the interconnect height should also not exceed 10 μm. This is possible with solder as well as adhesive bonding technologies. As originally published in the Pan Pacific Symposium Proceedings.